Impact of Parasitic and Load Current on the Attenuation of Motor Terminal Overvoltage in SiC-Based Drives

In SiC-based adjustable speed drives, the high voltage slew rate ( $dv\!/\!dt$ ) of switching transitions results in excessive overvoltage at motor terminals due to reflected voltages across drive power cables. Besides cable length, rise/fall times pulses are a key parameter quantify pulsewidth modulation (PWM) inverter-fed drives. These varying depending on load current and parasitic elements SiC mosfet s, that is, standard two-level converter typically nonuniform envelop terminals. This article analyses mechanism considering impact showing how they affect cable-fed The analysis is then extended mitigation using quasi-three-level (Q3L) as candidate filter-less approach with T-type converter. theoretical validated through experimental tests by Q3L show instantaneous value critically determines peak overvoltage, while it allows either full or partial when adopted.